1. Field of the Disclosure
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the manufacture of CMOS gate structures comprising a pre-doped gate material, such as a pre-doped polysilicon, with an improved uniformity of the dopant distribution.
2. Description of the Related Art
The fabrication of integrated circuits involves the formation of a very large number of circuit elements on a given chip area according to a specified circuit layout using a plurality of complex process steps. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operational speed and/or power consumption and/or cost efficiency. In this technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on an appropriate substrate, wherein the ongoing demand for an improved circuit functionality from a given chip area or a reduction of chip area while maintaining circuit functionality necessitates the scaling of transistor dimensions.
MOS transistors are formed in and on semiconductor regions defined in a substrate by isolation structures, such as shallow trench isolations and the like. A typical MOS transistor comprises PN junction regions that are separated from each other by a channel region, the conductivity of which is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The dimension of the channel region corresponding to the shortest distance between the two PN junction regions, which are also referred to as drain region and source region, is denoted as channel length and represents a dominant design characteristic of the MOS transistor. The channel width is the dimension of the channel in the substrate plane in the direction perpendicular to the length direction. The channel width is determined by the spacing between the isolation structures in this direction.
By reducing the channel length and width of the transistor, not only the transistor size but also the functional behavior thereof may be specifically designed so as to obtain a desired transistor performance. The channel length is associated with the gate length and may, in typical MOS transistors, be less than the gate length since the source and drain extension typically may extend below the gate electrode to a certain degree. Presently, a gate length of approximately 0.05 μm and less may be encountered in advanced CMOS devices.
Although the continuous size reduction of transistor elements has provided significant advantages in view of performance and/or power consumption, a plurality of issues has to be addressed so as to not unduly offset some of the advantages that are gained by the reduced dimensions of the circuit elements. For example, the fabrication of the circuit components having the critical dimensions, such as the gate electrode of the transistor element substantially determining the channel length, requires considerable efforts to reliably and reproducibly form these tiny circuit components. For instance, it is an extremely complex process to form gate electrodes having a gate length that is well below the wavelength of the UV radiation used to transfer a layout image from a reticle to a resist layer formed on the substrate.
A further difficulty arises from the fact that the PN junctions are defined by dopant profiles that are, at least partially, created by ion implantation and subsequent anneal cycles. Since, typically, reduced feature sizes necessitate higher dopant concentrations to compensate for the reduced conductivity owing to reduced cross-sectional areas, complex implantation cycles are required, wherein the vertical and lateral dopant profile has to be precisely controlled to achieve the desired transistor performance. Since the dopants implanted are subjected to diffusion upon elevated temperatures of the device during the further manufacturing processes, for activating the dopants and curing implantation-induced lattice damage, very strict requirements have to be met with respect to a thermal budget that describes the diffusivity of the dopants over time. The source/drain implantation is performed by using the gate electrode as an implantation mask, thereby providing an increased dopant level in the gate electrode, which is typically provided in the form of polysilicon.
A reduced transistor gate length also requires extremely shallow PN junctions in order to maintain the required controllability of the channel conductivity. Thus, the doping levels and profiles required in the drain and source regions of advanced transistor elements may necessitate implant processes that may be insufficient to achieve the required conductivity of the polysilicon gate electrode. Moreover, due to the non-uniform dopant distribution of these drain/source implantations, the resulting dopant concentration in the polysilicon gate electrode may not be appropriate for preventing undesired gate charge carrier depletion during transistor operation.
To overcome this problem, a polysilicon pre-doping process is typically performed after deposition of the polysilicon gate layer and prior to the gate patterning step. The polysilicon pre-doping is typically performed by ion implantation based on implantation parameters so as to substantially avoid penetration of dopants through the gate insulation layer, which otherwise may cause severe damage.
Consequently, the conventional approach may provide enhanced control of the electronic characteristics of the gate electrode structures of complex CMOS devices while, however, an increased degree of device failures may be observed after completion of the transistor structures, as will be described in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a top view of a CMOS device, that is, a semiconductor device including field effect transistors of different conductivity type, that is, P-channel transistors and N-channel transistors. The device 100 may comprise a substrate (not shown in FIG. 1a), above which is formed a semiconductor layer 103, in which are defined respective active regions or transistor regions 100A, 100B by means of an isolation structure 102. For example, the region 100A may correspond to an N-channel transistor while the region 100B may correspond to a P-channel transistor. Furthermore, as indicated by the dashed line 105, a gate electrode is to be formed so as to extend above the regions 100A, 100B so that a respective gate electrode material has to be doped according to the conductivity type of the respective transistors 100A, 100B as explained above.
FIG. 1b schematically illustrates a cross-sectional view of the device 100 as indicated by the line Ib in FIG. 1a. As illustrated, in the manufacturing stage shown, the device 100 comprises a substrate 101, which may represent any appropriate carrier material for forming thereabove the semiconductor layer 103, which may typically be a silicon layer since the vast majority of complex CMOS devices is presently, and will be in the near future, made of silicon due to the superior availability and the well-understood characteristics thereof. The substrate 101 in combination with the semiconductor layer 103 may form a “bulk” configuration in which the semiconductor layer 103 may represent an upper portion of the substantially crystalline material of the substrate 101, while, in other cases, a silicon-on-insulator (SOI) configuration may be used in which a buried insulating layer (not shown) may be positioned between the substrate 101 and the semiconductor layer 103. Furthermore, a gate insulation layer 106A is formed on the semiconductor layer 103 and, depending on the process for forming the gate insulation layer 106A, i.e., deposition or oxidation, the layer may or may not be formed on the isolation structure 102. For example, the gate insulation layer 106A may typically be comprised of silicon dioxide with an appropriate thickness corresponding to the overall characteristics of the transistors 100A, 100B. Moreover, a polysilicon layer 105A is formed on the gate insulation layer 106A with an appropriate thickness as required for the further processing for forming the gate electrode 105. Furthermore, an implantation mask 107, such as a resist mask, is formed above the device 100 such that the transistor region 100B may be covered, while the transistor region 100A may be exposed to an ion bombardment 108 for introducing a desired dopant species, such as an N-type dopant species.
The semiconductor device 100 as shown in FIGS. 1a and 1b may be formed on the basis of the following conventional process techniques. After providing the substrate 101 having formed thereabove the semiconductor layer 103, depending on the overall device strategy, the isolation structure 102 may be formed, for instance, by well-established lithography techniques for providing an etch mask, followed by an etch process for forming respective trenches in the semiconductor layer 103 down to a desired depth. Thereafter, an appropriate insulating material, such as silicon dioxide, possibly in combination with silicon nitride, may be deposited in order to fill the respective trenches with an insulating material. Next, excess material may be removed, for instance by etching, chemical mechanical polishing (CMP) and the like, thereby also providing an enhanced surface topography for the subsequent process steps. It should be appreciated that, in advanced integrated circuits, minimum feature sizes have reached a deep sub-micron range, thereby also requiring significant efforts in terms of suppressing contamination of the device 100, although the number of process steps may have increased with increasing complexity of the semiconductor devices. For this reason, exposed surface portions of a semiconductor device may have to be subjected to efficient cleaning processes in order to remove contaminations, such as organic species, metallic species and the like, which may otherwise have a significant influence on the further processing of the device. For example, the complex etch recipes typically used in patterning advanced features, such as the isolation structures 102 and also subsequent structures, such as the gate electrode 105, and also steps such as CMP, may result in a significant surface contamination in the form of organic etch residues, defect particles and the like, thereby requiring efficient cleaning strategies for which a plurality of efficient wet chemical processes have been established. Thus, prior to the formation of the gate insulation layer 106A, a respective wet chemical cleaning process may be performed. Thereafter, the gate insulation layer 106A may be formed, for instance, by oxidation, possibly in combination with deposition, depending on the overall requirements. Thereafter, the polysilicon layer 105A may be formed, for instance by low pressure chemical vapor deposition (LPCVD) based on well-established deposition recipes. Next, the resist mask 107 may be formed by photolithography and the ion implantation process 108 may be performed on the basis of appropriately selected implantation parameters so as to introduce a moderate dopant concentration into the exposed portion of the polysilicon layer 105A down to a specified depth, which is typically selected such that significant penetration of the gate insulation layer 106A and the underlying silicon material may be avoided. It should be appreciated that, prior to or after forming the isolation structure 102, respective implantation sequences may be performed to define the required base doping in the respective transistors 100A, 100B. In the example shown, it may be assumed that the transistor 100A may receive a P-type dopant so as to form an N-channel transistor by defining highly N-doped drain and source regions in a later manufacturing stage. Similarly, the transistor 100B may have received an N-type dopant species in order to form a P-channel transistor by defining heavily P-doped drain and source regions in a later stage.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage, in which an implantation mask 109 covers the region of the transistor 100A, while exposing the region of the transistor 100B during a further implantation process 110 for introducing a P-type dopant species into the exposed portion of the polysilicon layer 105A. Also, in this case, appropriately selected implantation parameters, such as energy and dose, may be selected so as to suppress undue penetration of the underlying gate insulation layer 106A and the semiconductor layer 103. After the implantation process 110, the implantation mask 109 may be removed and the further processing may be continued, for instance, by cleaning the resulting surface and depositing an anti-reflective coating (ARC) material, if required, followed by a mask material, such as resist and the like, for forming an appropriate etch mask for patterning the polysilicon layer 105A. For this purpose, well-established process techniques may be used. Thereafter, a sophisticated etch process may be performed by using plasma assisted and wet chemical etch techniques for patterning the polysilicon layer 105A, while using the gate insulation layer 106A as an etch stop material.
FIG. 1d schematically illustrates a cross-sectional view according to the line Id, as illustrated in FIG. 1a, after the etch process and after the removal of any unwanted materials, such as photoresist, any hard mask material and/or ARC material and the like. Thus, as illustrated, the transistor 100A comprises the gate electrode 105 with a gate length, i.e., in FIG. 1d, the horizontal extension of the gate electrode 105, in accordance with the design rules and the process variations occurring during the previously described patterning sequence. Furthermore, as previously explained, the plurality of the preceding process steps may require an additional cleaning process 111 in the form of a wet chemical step to efficiently remove contamination prior to performing subsequent process steps. For this purpose, a plurality of wet chemical solutions have been established, wherein, for instance, a mixture of ammonia (Nh3) and hydrogen peroxide (H2O2) (APM) has proven to be a highly efficient cleaning agent. Thus, during the wet chemical cleaning process 111, APM may be supplied with a specific concentration and at a predefined temperature in order to efficiently remove any contaminants. However, although APM represents a highly efficient wet chemical cleaning agent, a reaction rate may significantly depend on the electrochemical conditions during the etch process, which may sensitively depend on the presence of any metal residues, wherein it has been observed that APM may initiate extensive etching of polysilicon material in the presence of even very low metallic surface contaminations. Consequently, depending on the degree of surface contamination by any metal residues, a more or less pronounced attack of the gate electrode 105 may occur during the wet chemical cleaning process 111. After the process 111, the further processing may be continued on the basis of well-established CMOS techniques.
FIG. 1e schematically illustrates the transistor 100A in an advanced manufacturing stage. As illustrated, the transistor 100A comprises a spacer structure 112 on sidewalls of the gate electrode 105, which has formed therein a metal silicide region 114. Respective metal silicide regions 114 may also be formed in drain and source regions 113, which laterally enclose a channel region. In the example shown, the transistor 100A represents an N-channel transistor so that the drain and source regions 113 as well as an upper portion of the gate electrode 105 may comprise a moderately high concentration of an N-dopant species, while a lower portion of the gate electrode 105, indicated as n−, may be doped with a concentration as provided by the implantation process 108 (FIG. 1b) in order to enhance the electrical characteristics of the gate electrode 105. Furthermore, as previously indicated, in some cases, a significant etch damage may be observed in the gate electrode 105, which is assumed to be caused by the wet chemical cleaning process 111 on the basis of APM, as previously discussed. Consequently, the damaged carrier 105B may significantly affect the overall characteristics of the gate electrode 105 and thus of the transistor 100A, which may lead to increased yield losses in sophisticated CMOS devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.